A rapidly increasing complexity of VLSI designs and the associated test costs have generally rendered test data compression a de facto standard. In this test environment, captured responses can be taken through a response compactor, compressing the test responses. While test time and data volume can be thus reduced, the consequent information loss inevitably can reflect a loss in test quality. Certain errors that can be observable in the original scan responses can become unobserved in the compacted responses. Observability loss can be a consequence of multiple errors masking out the effect of each other, producing the expected values in the compressed response, or of the ambiguity induced by unknown response bits (x's) that can take on either binary value upon arbitrary initialization. Un-initialized memory elements such as, e.g., RAMs, multi-cycle paths, or bus contentions in a design can constitute potential sources for unknown values, which may propagate into a scan cell during test. Depending on the structure of the response compactor, these x's can prevent some errors that have been captured in other scan cells from being observed at the compactor outputs.
Sequential compaction circuitries, such as, e.g, multiple input single registers (MISRs), can be utilized for compressing the scan responses into a signature that can be observed at the end of the test application process. Unknown response bits can corrupt the signature, for example, if they propagate into the MISR. The fact that a single x can corrupt the MISR content can stem from its sequential nature in accumulating its signature. An x-masking circuitry, e.g., one capable of delivering per-scan and/or per-chain replacement of response x's with known constant values based on control bits delivered from Automatic Test Equipment (ATE), can be utilized in order to prevent the corruption of the signature. A costly alternative can be inserting test points to mask x's right at their sources at the expense of area cost and performance degradation. Combinational compaction solutions, e.g., XOR-based, can also be utilized for response compaction. Some of these techniques, for example, can build the response compactor based on fault sensitization information under a particular fault model assumption, while response unknown bit and unmodeled defect coverage issues can be overlooked. Similarly, utilization of a given test set to build compactors, or to reorder x-capturing scan cells can offer improved observability, while dependence on a test set can complicate the implementation of these solutions. Test set and fault model independent response compaction techniques have also been described, which can deliver some x-mitigation capabilities. Further, selective masking/observing of chains, and further optimizations by grouping together of cells that have similar masking requirements over an interval enabled by the clustered behavior of x's can ensure the observation of the targeted faults, while potentially missing unmodeled defects. Correlation among x's can be exploited to reduce the amount of mask control data.
These compaction techniques can bear a particular resistance characteristic to unknown bits. The density and distribution of x's can determine the test quality delivered by these schemes. In the presence of an x-distribution where the corruption effect of x's is widely spread, combinational compactors typically produce mostly x's at their outputs, while sequential ones with masking-support often produce responses that are over-masked. Thus, in both types of compactors, the fault/defect information in x-free scan cells can be compromised, resulting in poor scan cell observability, and, hence, degradation in test pattern effectiveness. A test pattern inflation and hence a test cost increase may ensue upon attempts on restoring the compromised quality levels. Further, high quality screening of chips may utilize aggressive solutions such as faster-than-at-speed testing, which can generate responses with high density of unknown x's.
In an effort to cope with increasing test costs, test data compression solutions can be employed, wherein a few number of scan-in channels drive a larger number of internal scan chains through a decompression block, while the responses collected from the internal scan chains can be taken through a compactor block that drives a fewer number of scan-out channels. Driving a larger number of internal scan chains from a fewer number of scan channels can reduce the depth of the scan chains, decreasing the number of shift (e.g., scan) operations per scan pattern, and hence shortening the test application time.
Certain logic blocks, such as RAMs or tri-state buses, and setup requirement violator paths may produce values that are unknown during simulation time, and are known only after the chip has been powered up, where these values can change from one chip to another. Test patterns may propagate these unknown bits (x's) to the outputs, capture them in scan cells, and produce response patterns with x's. While the observation of individual known (non-x) bits in the response can assist with an indication as to whether the chip under test is defective, a compression of x's and non-x's altogether through a response compactor can weaken this screening process. The ambiguity induced by the response x's results in the loss of some of the known bits, which can have otherwise manifested the effect of the defects in the chip under test. Test quality, may be degraded as a result.
Accordingly, there can be a need to address and/or overcome at least some of the above described deficiencies and issues.